In general, there may be a variety of technologies in semiconductor industry to integrate a plurality of field effect transistors (FETs) into a carrier or wafer. The field effect transistors are typically electrically isolated from each other via a dielectric material disposed within the carrier between respectively adjacent FETs. A field effect transistor (FET) typically includes a body region (e.g. p-type or n-type), the body region connecting a source region with a drain region, and a gate region controlling the body region between the source region and the drain region. An electrical field is usually induced into the body region via the gate (e.g. via applying a voltage at the gate region, wherein the gate region is electrically isolated from the body region via a dielectric layer) such that the electrical conductivity of the body region may be varied to control a current flow between the source region and the drain region. A plurality of FETs (e.g. metal-oxide-semiconductor field-effect transistors (MOSFETs)) is typically integrated into a carrier or wafer, wherein the FETs may be separated from each other via so-called shallow trench isolation (STI) (e.g. also known as box isolation technique). However, other processes like local oxidation of silicon (LOCOS) or deep trench isolation may also be used to electrically separate the body regions or the active regions of adjacent FETs integrated into a carrier or wafer from each other.